Tapas Kumar Maiti

PhD (Electronics & Telecommunication Engineering), Jadavpur University, Kolkata


Dr. Tapas Kumar Maiti moved from Hiroshima University, Japan to DA-IICT, India where he is working as an Associate Professor, since Jun. 2019. He has strong teaching and research experiences (9.4 years overseas) in the areas of SPICE for VLSI Circuits and Devices, Humanoid Robot, and Cyber-Physics. He spent 7.4 years at Hiroshima University where he worked as an Associate Professor, since Apr. 2017, an Assistant Professor for two years, and a researcher for three years. Prior to that he worked as a postdoctoral fellow for two years at McMaster University, collaboration with ARISE Technology Corporation of Waterloo, Canada. He solves society’s issues creatively by developing model, software and hardware products, particularly micro-/nano-electronics driven robot system development. He has more than 100 publications. He received ICMM2017 Excellent Presentation Award at Tokyo, Japan and IAAM Scientist Medal, Stockholm, Sweden in 2017. He also served as a publication chair, technical program committee member, and session chair in various international conferences, reviewer in several international journals. He led numerous projects involving TCAD for Nano Engineered Semiconductor Devices, SPICE for VLSI Circuit, Virtual Laboratory, Artificial Organ, and Humanoid Robot [funded by government agencies, university, industry, and others]. He is a member of IEEE, IAAM, and Life Member IEI.

He joined Dept. of Electronics and Electrical Communication Engineering, IIT-Kharagpur in 2005 to carry out his research work on Nano Engineered Silicon CMOS Transistors [TCAD to SPICE] and completed PhD degree in Engineering from the Dept. of Electronics and Telecommunication Engineering at Jadavpur University, Kolkata, India in 2009.


SPICE for VLSI Circuits, Humanoid Robot, Cyber-Physics


  • N. Rohbani, H. Gau, S. Mohammadinejad, T. K. Maiti, D. Navarro, M. Miura-Mattausch, H. J. Mattausch, and H. Takatsuka, “Power Reduction and BTI Mitigation of Data-Cache Memory Based on the Storage Management of Narrow-Width Values,” IEEE Transactions on Very Large Scale Integration Systems (VLSI), 2019.
  • M. Miura-Mattausch, H. Kikuchihara, T. K. Maiti, D. Navarro, and H. J. Mattausch, “Modeling of Carrier Trapping and Its Impact on Switching Performance,” IEEE Journal of the Electron Devices Society, pp. 1056-1063, vol. 6, Aug. 2018.
  • T. K. Maiti, Y. Ochi, D. Navarro, M. Miura-Mattausch, and H. J. Mattausch, “Walking Robot Movement on Non-Smooth Surface Controlled by Pressure Sensor,” Advanced Material Letters, pp.123-127, vol. 9, no. 2, 2018.
  • M. Miura-Mattausch, H. Miyamoto, H. Kikuchihara, T. K. Maiti, N. Rohbani, D. Navarro, H.J. Mattausch, “Compact Modeling of Dynamic Trap Density Evolution for Predicting Circuit-Performance Aging,” Microelectronics Reliability, pp.64–175, vol.80, 2018.
  • T. K. Maiti, L. Chen, H. Zenitani, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Compact Electro-Mechanical-Fluidic Model for Actuated Fluid Flow System,” IEEE Journal on Multiscale and Multiphysics Computational Techniques, pp.124-133, vol. 2, Jul. 2017.
  • T. K. Maiti, L. Chen, H. Zenitani, H. Miyamoto, M. Miura-Mattausch, and H. J. Mattausch, “Physically Based Compact Mobility Model for Organic Thin-Film Transistor,” IEEE Transactions on Electron Devices, vol. 63, Iss. 5, pp. 2057-2065, May 2016.
  • T. K. Maiti, T. Hayashi, L. Chen, H. Mori, M. J. Kang, K. Takimiya, M. Miura-Mattausch, and H. J. Mattausch, “A Surface Potential Based Organic Thin-Film Transistor Model for Circuit Simulation Verified With DNTT High Performance Test Devices,” IEEE Transaction on Semiconductor Manufacturing, vol. 27, Iss. 2, pp.159-168, May 2014.


  • Introduction to VLSI Circuit
  • Embedded Systems for Smart Application